{"id":64323,"date":"2018-04-28T07:04:24","date_gmt":"2018-04-28T07:04:24","guid":{"rendered":"https:\/\/www.biphoo.com\/bipnews\/?p=64323"},"modified":"2018-04-28T07:04:24","modified_gmt":"2018-04-28T07:04:24","slug":"intel-delays-broken-10nm-into-2019-hires-jim-keller-to-fix-it","status":"publish","type":"post","link":"https:\/\/www.biphoo.com\/bipnews\/technology\/intel-delays-broken-10nm-into-2019-hires-jim-keller-to-fix-it.html","title":{"rendered":"Intel Delays Broken 10nm Into 2019, Hires Jim Keller to Fix It"},"content":{"rendered":"<h2 style=\"text-align: justify\"><span style=\"font-size: 18pt\"><strong><span style=\"font-family: Arial, Helvetica, sans-serif\">Intel Delays Broken 10nm Into 2019, Hires Jim Keller to Fix It<\/span><\/strong><\/span><\/h2>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">Last year, Intel told investors and the press that it had begun early shipments on 10nm, though it refused to identify which parts this applied to, or when we would see volume shipments. Similarly, the company declared its 8th Generation Core family would comprise multiple chips across 14nm, 14nm+, 14nm++, and 10nm. Now, Intel has announced that it will delay volume shipment on 10nm into 2019, rather than ramping in the first half of 2018.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">We continue to make progress on our 10-nanometer process. We are shipping in low volume and yields are improving, though the rate of improvement is slower than we anticipated. As a result, volume production is moving from the second half of 2018 into 2019. We understand the yield issues and have defined improvements for them, but they will take time to implement and qualify. We have leadership products on the roadmap that continue to take advantage of 14-nanometer, with Whiskey Lake for clients and Cascade Lake for the data center coming later this year.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">Krzanich then argues that these delays are more-or-less business as usual, and that Intel is still delivering real gains following Moore\u2019s Law. He states:<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">For example, 14-nanometer process optimizations and architectural improvements have resulted in performance gains of more than 70 percent since the first 14-nanometer products were launched. We combine these advances in manufacturing technology and architecture to produce truly leadership products. And it\u2019s that product leadership that ultimately matters most to our customers and end users.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">Under questioning, Krzanich acknowledged that the difficulties with 10nm are related to not having EUV to use yet, but claimed that Intel still has \u201cprocess and performance leadership,\u201d and again stated that the company had done \u201c70 percent improvements\u201d to 14nm over its lifetime. He also argued that Intel\u2019s 10nm problems were related to its aggressive scaling \u2014 something that may well be true, given that Intel did set aggressive 10nm targets. But with respect to Brian Krzanich, that 70 percent improvement figure isn\u2019t something Intel is going to be able to keep duplicating, and it\u2019s not clear that it\u2019s a useful data point in this context. The slideshow below contains information on Intel\u2019s 10nm node that the company has previously revealed; though obviously we now expects these parts no earlier than 2019.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">The 70 percent gain that Intel is talking about appears to be related to its decision to finally ship higher core counts in mobile. We\u2019ve mapped the overall progression from 5th Generation Core (Broadwell, first-generation 14nm) to 8th Generation Core (Coffee Lake, 14nm++) below, with a Kaby Lake 7th Gen chip tossed in for comparison\u2019s sake.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">Intel absolutely got some clock improvements courtesy of its evolved 14nm process \u2014 the Core i7-7650U is clocked 1.14x higher than the i7-5650U, and peak single-core frequencies are significantly higher on the 8th Generation chip compared with OG 14nm. 8th Generation reviews and benchmarks also suggest that the switch to quad-cores resulted in substantially higher performance within a similar battery life, making these parts a win for Intel all the way around. Well and good.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">But there are limits to how many cores you can pack into a CPU while keeping the frequency high, no matter how aggressively you tune your process. Stepping up to a six-core mobile chip wouldn\u2019t get Intel the same size increase (it\u2019s an intrinsically smaller gain, in percentage terms), and it would come with tighter limits on minimum and maximum clock. It\u2019s also likely that Intel, which had no initial plans to iterate on 14nm for three generations, has largely tapped out the improvements it can squeeze from the node.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">Evaluating Intel\u2019s Explanations<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">On the one hand, everything Krzanich said on the conference call makes perfect sense. As we\u2019ve written before, node shrinks have become more difficult as geometries have gotten smaller. Not having EUV available means semiconductor firms must use strategies like multi-patterning, and multi-patterning makes lithography costs explode. Intel\u2019s claim to have a path to 7nm without EUV was always a little dubious, so it\u2019s not surprising to see the company struggling at 10nm. And while TSMC and Samsung have both been shipping 10nm for quite a while, Intel\u2019s 10nm node targets feature sizes that correspond to what the pure-play foundries are targeting for 7nm. One can persuasively argue that it took TSMC, GF, and Samsung years to match Intel\u2019s feature sizes, rather than the reverse (Intel 14nm \u2248 Foundry 10nm).<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">On the other hand, Intel launched 14nm back in 2014 with 10nm forecast for late 2016 or early 2017. Then that schedule slipped back to 2018. Now it\u2019s slipped back into 2019. Krzanich can talk up Intel\u2019s improvements to 14nm, but none of that changes the fact that the company has never needed five years for a node transition before. And even now, Intel isn\u2019t willing to say it\u2019ll launch on 10nm in H1 2019 \u2014 it\u2019s only saying \u201c2019.\u201d Intel\u2019s decision to hire former AMD Zen designer Jim Keller away from Tesla and install him as a senior VP in charge of silicon engineering also implies the company is looking to reassure investors that its 10nm ramps have its full attention. But regardless, we\u2019re now talking about whether Intel can match its competitors on feature sizes, not whether it\u2019ll continue to lead the industry.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 14pt\">It\u2019s unclear how these delays will impact Intel\u2019s efforts to deal with a resurgent AMD. We\u2019ve already heard rumors that the company is prepping an eight-core Coffee Lake \u2014 that could be the Whiskey Lake hardware Intel previously mentioned. AMD\u2019s Ryzen 2 is supposed to debut next year on 7nm, though we\u2019re not sure how well GF is executing on its own node ramps. Intel hadn\u2019t intended to ramp 10nm for desktops initially, so the delay may not have much impact on the desktop space. But delaying 10nm on mobile will make it easier for ARM vendors and AMD\u2019s own Ryzen Mobile parts to compete in that space throughout 2018.<\/span><\/p>\n<p style=\"text-align: justify\"><span style=\"font-family: Arial, Helvetica, sans-serif;font-size: 8pt\">Source:-https:\/\/www.extremetech.com\/computing\/268407-intel-delays-broken-10nm-into-2019-hires-jim-keller-to-fix-it<\/span><\/p>\n<div class=\"fb-background-color\">\n\t\t\t  <div \n\t\t\t  \tclass = \"fb-comments\" \n\t\t\t  \tdata-href = \"https:\/\/www.biphoo.com\/bipnews\/technology\/intel-delays-broken-10nm-into-2019-hires-jim-keller-to-fix-it.html\"\n\t\t\t  \tdata-numposts = \"10\"\n\t\t\t  \tdata-lazy = \"true\"\n\t\t\t\tdata-colorscheme = \"light\"\n\t\t\t\tdata-order-by = \"social\"\n\t\t\t\tdata-mobile=true>\n\t\t\t  <\/div><\/div>\n\t\t  <style>\n\t\t    .fb-background-color {\n\t\t\t\tbackground: #ffffff !important;\n\t\t\t}\n\t\t\t.fb_iframe_widget_fluid_desktop iframe {\n\t\t\t    width: 630px !important;\n\t\t\t}\n\t\t  <\/style>\n\t\t  ","protected":false},"excerpt":{"rendered":"<p>Intel Delays Broken 10nm Into 2019, Hires Jim Keller to Fix It Last year, Intel told investors and the press that it had begun early shipments on 10nm, though it refused to identify which parts this applied to, or when we would see volume shipments. Similarly, the company declared its [&hellip;]<\/p>\n","protected":false},"author":9,"featured_media":64324,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[13],"tags":[134680,692,14505,12073,14823],"class_list":["post-64323","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technology","tag-intel-delays-broken-10nm-into-2019-hires-jim-keller-to-fix-it","tag-latest-technology-news","tag-technology-news-headlines","tag-technology-news-today","tag-technology-news-usa"],"_links":{"self":[{"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/posts\/64323","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/users\/9"}],"replies":[{"embeddable":true,"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/comments?post=64323"}],"version-history":[{"count":0,"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/posts\/64323\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/media\/64324"}],"wp:attachment":[{"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/media?parent=64323"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/categories?post=64323"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.biphoo.com\/bipnews\/wp-json\/wp\/v2\/tags?post=64323"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}